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Data Sheet No.PD60221
IRS2011(S)PbF
Features
* * * * * * * * * * *
HIGH AND LOW SIDE DRIVER
Product Summary
VOFFSET IO+/VOUT ton/off Delay Matching 200 V max. 1.0 A /1.0 A typ. 10 V - 20 V 60 ns typ. 20 ns max.
Floating channel designed for bootstrap operation Fully operational up to +200 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Independent low-side and high-side channels Input logic HIN/LIN active high Undervoltage lockout for both channels 3.3 V and 5 V input logic compatible CMOS Schmitt-triggered inputs with pull-down Matched propagation delay for both channels RoHS compliant
Applications
* Audio Class D amplifiers * High power DC-DC SMPS converters * DC motor drive
Packages
Description
The IRS2011 is a high power, high speed power MOSFET driver with independent high and low-side referenced output IRS2011S IRS2011 channels, ideal for Audio Class D and DC-DC converter appli8-Lead SOIC 8-Lead PDIP cations. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an Nchannel power MOSFET in the high-side configuration which operates up to 200 V. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction.
Typical Connection
HIN LIN COM
200 V
5
HIN LIN COM
VS HO VB V CC
4
TO LOAD
8
LO
1
VCC
(Refer to Lead Assignments for correct configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
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IRS2011(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB VS V HO V CC VLO V IN dV s/dt PD RTHJA TJ TS TL
Definition
High-side floating supply voltage High-side floating supply offset voltage High-side floating output voltage Low-side fixed supply voltage Low-side output voltage Logic input voltage (HIN & LIN) Allowable offset supply voltage transient (Fig. 2) Package power dissipation @ TA = +25 C Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (8-lead DIP) (8-lead SOIC) (8-lead DIP) (8-lead SOIC)
Min.
-0.3 VB - 20 VS - 0.3 -0.3 -0.3 -0.3 -- -- -- -- -- -- -55 --
Max.
220 (Note 1) VB + 0.3 VB + 0.3 20 (Note 1) VCC +0.3 VCC +0.3 50 1.0 0.625 125 200 150 150 300
Units
V
V/ns W C/W
C
Note 1: All supplies are fully tested at 25 V and an internal 20 V clamp exists for each supply.
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. The VS and COM offset ratings are tested with all supplies biased at a 15 V differential.
Symbol
VB VS V HO V CC VLO V IN TA
Definition
High-side floating supply absolute voltage High-side floating supply offset voltage High-side floating output voltage Low-side fixed supply voltage Low-side output voltage Logic input voltage (HIN & LIN) Ambient temperature
Min.
VS + 10 Note 2 VS 10 0 COM -40
Max.
VS + 20 200 VB 20 V CC 5.5 125
Units
V
C
Note 2: Logic operational for VS of -5 V to +200 V. Logic state held for VS of -5 V to -VBS.
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IRS2011(S)PbF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, CL = 1000 pF, TA = 25 C unless otherwise specified. Figure 1 shows the timing definitions.
Symbol
ton t off tr tf DM1 DM2
Definition
Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time Turn-on delay matching | ton (H) - ton (L) | Turn-off delay matching | toff (H) - toff (L) |
Min. Typ. Max. Units Test Conditions
-- -- -- -- -- -- 60 60 25 15 -- -- 80 80 40 35 20 20 VS = 0V VS = 200V
ns
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, and TA = 25 C unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to COM and are applicable to all logic input leads: HIN and LIN. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
V IH V IL V OH VOL ILK IQBS IQCC IIN+ IINVBSUV+ VBSUVVCCUV+ VCCUVIO+ IO-
Definition
Logic "1" input voltage Logic "0" input voltage High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic "1" input bias current Logic "0" input bias current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold Output high short circuit pulsed current Output low short circuit pulsed current
Min. Typ. Max. Units Test Conditions
2.5 -- -- -- -- -- -- -- -- 8.3 7.5 8.3 7.5 -- -- -- -- -- -- -- 120 200 3 -- 9.0 8.2 9.0 8.2 1.0 1.0 -- 0.7 1.4 0.1 50 210 300 10 5.0 9.7 8.9 9.7 8.9 -- A -- VO = 0 V, PW = 10 s VO = 15 V, PW = 10 s V A V IO = 0 A IO = 20 mA VB=VS = 200 V VIN = 0 V or 3.3 V VIN = 3.3 V VIN = 0 V VCC = 10 V - 20 V
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IRS2011(S)PbF
Functional Block Diagram
VB HIGH VOLTAGE LEVEL SHIFT CIRCUIT UV DETECT UV Q S R VS
3V S-TRIGGER HIN LOW VOLTAGE LEVEL SHIFT BUFFER
HO
VCC 3V S-TRIGGER LIN LOW VOLTAGE LEVEL SHIFT UV DETECT LO DELAY COM
Lead Definitions
Symbol Description
HIN LIN VB HO VS VCC LO COM Logic input for high-side gate driver output (HO), in phase Logic input for low-side gate driver output (LO), in phase High-side floating supply High-side gate drive output High-side floating supply return Low-side supply Low-side gate drive output Low-side return
Lead Assignments
5 HIN 6 LIN 7 COM 8 LO
VS 4 HO 3 VB 2 VCC 1
5 HIN 6 LIN 7 COM 8 LO
VS 4 HO 3 VB 2 VCC 1
8-Lead SOIC
8-Lead PDIP
IRS2011S Part Number
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IRS2011
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IRS2011(S)PbF
50%
50%
HIN / LIN
trise 90% ton(H) 10% 90% toff(H) 10% tfall
HO
DM1 90% ton(L) 10% toff(L)
DM2
LO
Figure 1. Timing Diagram
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IRS2011(S)PbF
Turn-O n Propagation Delay (ns)
Turn-O n Propagation Delay (ns)
500 400 300 200 100
Max. Typ.
500 400 300 200 100 0 10 12 14 16 18 20
Max. Typ.
0 -50
-25
0
25
50
75
100
125
Temperature ( oC) Figure 2A. Turn-On Propagation Delay vs. Temperature
V BIAS Supply Voltage (V) Figure 2B. Turn-On Propagation Delay vs. Supply Voltage
Turn-O ff Propagation Delay (ns)
Turn-O ff Propagation Delay (ns)
500 400 300 200 100
Max. Typ.
500 400 300 200 100 0 10 12 14 16 18 20
Max. Typ.
0 -50
-25
0
25
50
75
100
125
Temperature ( oC) Figure 3A. Turn-Off Propagation Delay vs. Temperature
V BIAS Supply Voltage (V) Figure 3B. Turn-Off Propagation Delay vs. Supply Voltage
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IRS2011(S)PbF
100
Turn-O n Rise Time (ns)
100
Turn-O n Rise Time (ns)
80 60 40 20
Max.
80 60 40 20 0
Max.
Typ.
Typ.
0 -50
-25
0
25
50 (oC)
75
100
125
10
12
14
16
18
20
Temperature
V BIAS Supply Voltage (V) Figure 4B. Turn-On Rise Time vs. Supply Voltage
Fiure 4A. Turn-On Rise Time vs.Temperature
50
Turn-O ff Fall Time (ns)
50
Turn-O ff Fall Time (ns)
40 30 20 10
Typ. Max.
40
Max.
30 20 10 0
Typ.
0 -50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (oC) Figure 5A. Turn-Off Fall Time vs. Temperature
V BIAS Supply Voltage (V) Figure 5B. Turn-Off Fall Time vs. Supply Voltage
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IRS2011(S)PbF
Turn-On Delay Matching Time (ns) Turn-on Delay Matching Time (ns
Turn-On Delay Matching Time (ns) Turn-off Delay Matching Time (ns
50 40 30
Max.
50 40 30
Max.
20 10 0 -50
20 10 0 -50
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (oC)
Figure 6A. Turn-On Delay Matching Time Figure 6A. Turn-on Delay Matching Time vs. Temperature vs. Temperature
V CC Supply Voltage (V)
Figure 6B. Turn-on Delay Matching Time Figure 6B. Turn-On Delay Matching Time vs. Supply Voltage vs. Supply Voltage
Turn-Off Delay Matching Time (ns) Turn-off Delay Matching Time (ns
Turn-Off Delay Matching Time (ns) Turn-off Delay Matching Time (ns
50 40 30
Max.
50 40 30
Max.
20 10 0 -50
20 10 0 -50
-25
0
25
50 (oC)
75
100
125
-25
0
25
50
75
100
125
Temperature
V CC Supply Voltage (V) Figure 7B. Turn-Off Delay Matching Time Figure 7B. Turn-off Delay Matching Time vs. Supply Voltage vs. Supply Voltage
Figure 7A. Turn-off Delay Matching Time Figure 7A. Turn-Off Delay Matching Time vs. Temperature vs. Temperature
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IRS2011(S)PbF
5 Logic "1" Input Voltage (V) Logic "1" Input Voltage (V) 4 3 2 1 0 -50
Min.
5 4 3 2 1 0 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (oC) Figure 8A. Logic "1" Input Voltage vs. Temperature V CC Supply Voltage (V) Figure 8B. Logic "1" Input Voltage vs. Supply Voltage
Min.
5 Logic "0" Input Voltage (V) 4 3 2 1
Max.
5 Logic "0" Input Voltage (V) 0 25 50 (oC) 75 100 125 4 3 2 1
Max.
0 -50
0 -25 10 12 14 16 18 20 Temperatre V CC Supply Voltage (V) Figure 9B. Logic "0" Input Voltage vs. Supply Voltage
Figure 9A. Logic "0" Input Voltage vs. Temperature
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IRS2011(S)PbF
High L evel Output Vo ltage (V)
4.0 3.0 2.0 1.0 0.0 -50
High L evel Output Vol tage (V)
5.0
5.0 4.0 3.0 2.0 1.0 0.0 10 12 14 16 18 20 V BAIS Supply Voltage (V) Figure 10B. High Level Output Voltage vs. Su pply Voltage (Io = 0 mA)
Max.
M ax
-25
0
25
50
75
100
125
Temperature (oC) Figure 10A. High Level Output Voltage vs. Te mperature (Io = 0 mA)
Low Level O utput Voltage (V)
0.5 0.4 0.3 0.2
Max.
0.5 Low Level O utput Voltage (V) -25 0 25 50 75 100 125 0.4 0.3 0.2
Max.
0.1 0.0 -50
0.1 0.0 10 12 14 16 18 20 V CC Supply Voltage (V) Figure 11B. Low Level Output vs. Supply Voltage
Temperature (oC) Figure 11A. Low Level Output vs.Temperature
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IRS2011(S)PbF
O ffs et Supply Leakage Current (A)
500 400 300 200 100
O ffset Supply Leak age Current ( A)
500 400 300 200
Max.
Max.
100 0 50 100 150 200 250 300
0 -50
-25
0
25
50
75
100
125
Temperature (oC) Figure 12A. Offset Supply Leakage Current vs. Temperature
V B Boost Voltage (V) Figure 12B. Offset Supply Leakage Current vs. Supply Voltage
600
V BS Supply Current ( A)
600 500 400 300 200 100 0
Max. Typ.
V BS Supply Current (A)
500 400 300 200 100 0 -50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (oC) Figure 13A. V BS Supply Current vs. Temperature
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V BS Supply Voltage (V) Figure 13B. V BS Supply Current vs. Supply Voltage
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IRS2011(S)PbF
600
V CC Supply Current (A)
600
480 360
Max.
V CC Supply Current (A)
480 360 240 120
Typ.
240 120 0 -50
Typ.
Max.
0
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (oC) Figure 14A. V CC Supply Current vs. Temperature
V CC Supply Voltage (V) Figure 14B. V CC Supply Current vs. Supply Voltage
100
Logic "1" Input Current (A)
100
Logic "1" Input Current (A)
80 60 40 20 0 -50
Max. Typ.
80 60 40 20 0
Max. Typ.
-25
0
25
50 (oC)
75
100
125
10
12
14
16
18
20
Temperature
V CC Supply Voltage (V) Figure 15B. Logic "1" Input Current vs. Supply Voltage
Figure 15A. Logic "1" Input Current vs. Temperature
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IRS2011(S)PbF
Logic "0" Input Bias Current (A)
Lo gic "0" Input Bias Current (A)
6 5 4 3 2 1 0 -50 Max
6 5 4 3 2 1 0 10 12 14 16 18 20 Supply Voltage (V) Max
-25
0
25
50
75
100
125
Temperature (C)
Figure 16A. Logic "0" Input Bias Current vs. Temperature
Figure 16B. Logic "0" Input Bias Current vs. Voltage
12 UV Threshold (-) (V) 10.8 UV Threshold (+) (V)
Max.
12 10.8 9.6
Max.
9.6
Typ.
8.4
Min.
8.4
Typ.
7.2 6 -50
7.2 6 -50
Min.
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (oC) Figure 17. VCC and VBS Undervoltage Threshold (+) vs. Temperature
Temperature (oC) Figure 18. V CC and V BS Undervoltage Threshold (-) vs. Temperature
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IRS2011(S)PbF
5 O utput Source Current (A) 4 3 2 1
Typ.
5 O utput Source Current (A) 4 3 2
Typ.
1 0 10 12 14 16 18 20 V BIAS Supply Voltage (V) Figure 19B. Output Source Current vs. Supply Voltage
0 -50
-25
0
25
50
75
100
125
Temperature (oC) Figure 19A. Output Source Current vs. Temperature
5
5
O utput Sink Current (A)
4 3 2 1
Typ.
O utput Sink Current (A)
4 3 2 1 0
Typ.
0 -50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (oC) Figure 20A. Output Sink Current vs. Temperature
Supply Voltage (V) Figure 20B. Output Sink Current vs. Supply Voltage
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IRS2011(S)PbF
Maximum V Negative Offset (V) S
0 -3 -6 -9 -12 -15 10 12 14 16 18 20 V BS Floating Supply Voltage (V) Figure 21. Maxim um V S Negative Offset vs V BS Floating Supply Voltage
65
Temperature (oC) o Temperature ( C)
65 55 45 35 25 15 1 10 100 1000 1 10 100 1000 Frequency (kHz) Frequency (kHz) Figure 23. IRS2011S vs. Frequency (IRFBC30) Rgate=22 , V CC=12 V
55 45 35 25 15
Temperature (oC)
Figure 22. IRS2011S vs. Frequency (IRFBC20) Rgate=33 , V CC=12 V
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IRS2011(S)PbF
65
65 55
55
Temperature (oC)
Temperature (oC)
Temperature (C)
45
45 35 25 15
35
25
15 1 10 100 1000
1
10
100
1000
Frequency (kHz) Figure 24. IRS2011s vs. Frequency (IRFBC40) Figure 24. IRS2011S vs. Frequency (IRFBC40) Rgate=15 , V CC=12 V
Frequency (kHz)
Figure 25. IRS2011S vs. Frequency (IRFB23N15D) Rgate=10 , V CC=12 V
65
Temperature (oC)
55 45 35 25 15 1 10 100 1000 Frequency (kHz) Figure 26. IRS2011S vs. Frequency (IRFB4212) Rgate=10 , V CC=12 V
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IRS2011(S)PbF
Case outlines
D A 5 B
FOOTPRINT 8X 0.72 [.028]
DIM A b
INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
A1 .0040 c
8 6 E 1
7
6
5 H 0.25 [.010] A
6.46 [.255]
D E e e1 H K L
8X 1.78 [.070]
2
3
4
.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X e
3X 1.27 [.050]
y
e1 A C 0.10 [.004] 8X b 0.25 [.010]
NOTES: 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
K x 45 y
A1 CAB
8X L 7
8X c
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE.
8-Lead SOIC
01-6027 01-0021 11 (MS-012AA)
8-Lead PDIP
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01-6014 01-3003 01 (MS-001AB)
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IRS2011(S)PbF
Tape & Reel 8-lead SOIC
LOAD ED TA PE FEED DIRECTION
B
A
H
D
F
C
N OT E : CO NTROLLING D IMENSION IN M M
E
G
C A R R I E R T A P E D IM E N S I O N F O R 8 S O I C N M etr ic Im p e r ia l Co d e M in M ax M in M ax A 7 .9 0 8 .1 0 0 . 31 1 0 .3 1 8 B 3 .9 0 4 .1 0 0 . 15 3 0 .1 6 1 C 11 .7 0 1 2. 30 0 .4 6 0 .4 8 4 D 5 .4 5 5 .5 5 0 . 21 4 0 .2 1 8 E 6 .3 0 6 .5 0 0 . 24 8 0 .2 5 5 F 5 .1 0 5 .3 0 0 . 20 0 0 .2 0 8 G 1 .5 0 n/ a 0 . 05 9 n/ a H 1 .5 0 1 .6 0 0 . 05 9 0 .0 6 2
F
D
C B
A
E
G
H
R E E L D IM E N S I O N S F O R 8 S O IC N M etr ic Im p e r ia l Co d e M in M ax M in M ax A 32 9. 6 0 3 3 0 .2 5 1 2 .9 7 6 1 3 .0 0 1 B 20 .9 5 2 1. 45 0 . 82 4 0 .8 4 4 C 12 .8 0 1 3. 20 0 . 50 3 0 .5 1 9 D 1 .9 5 2 .4 5 0 . 76 7 0 .0 9 6 E 98 .0 0 1 0 2 .0 0 3 . 85 8 4 .0 1 5 F n /a 1 8. 40 n /a 0 .7 2 4 G 14 .5 0 1 7. 10 0 . 57 0 0 .6 7 3 H 12 .4 0 1 4. 40 0 . 48 8 0 .5 6 6
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IRS2011(S)PbF
LEADFREE PART MARKING INFORMATION
Part number
IRxxxxxx S YWW? ?XXXX
Lot Code (Prod mode - 4 digit SPN code) IR logo
Date code
Pin 1 Identifier ? P MARKING CODE Lead Free Released Non-Lead Free Released
Assembly site code Per SCOP 200-002
ORDER INFORMATION
8-Lead PDIP IRS2011PBF 8-Lead SOIC IRS2011SPbF 8-Lead SOIC Tape & Reel IRS2011STRPbF
SOIC-8 package is MSL2 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found on IR's Web Site http://www.irf.com/ WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 12/4/2006
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